A Design Flow for Asynchronous Dynamic Logic and Standard Synthesis Tools

For high performance designs, dynamic logic styles are in the focus due to the promising high reachable frequencies. True Single Phase Clock (TSPC) logic yields easy to design circuits with standard cells and high speed potential. The disadvantages are a difficult clock tree design and high power consumption. Asynchronous logic has the potential to solve these problems. Asynchronous Chain (AC)-TSPC logic assembles small asynchronous chains of dynamic logic gates into one period of the global clock. The results are a shorter latency for calculations, power reduction due to smaller clock load and due to no need for latches, and a simpler clock distribution network due to increased clock skew tolerance and due to the reduced clock load. Current high level synthesis tools do not support automatic synthesis and verification of asynchronous dynamic logic. This paper presents a complete design flow of Asynchronous Chain (AC)-TSPC logic. We use the toolset DYNAMIC, which realizes a transformation of a combinational circuit into a pipelined structure, and the tool AC-DYNAMIC, which implements a splitting of a pipelined structure into an asynchronous clocked structure. Further, AC-DYNAMIC verifies the timing behavior, and realizes optimizations. The design flow is exemplarily utilized for a 32-bit-single-error-correcting circuit. Utilized Synopsys Tools: Design Compiler, Library Compiler, HSPICE